During conventional semiconductor processing, plasma techniques are routinely employed, particularly in manufacturing Very Large Scale Integrated (VLSI) devices. Such conventional plasma techniques comprise etching various films, including polycrystalline silicon, oxides and metals. Plasma techniques are also conventionally employed for oxide deposition, sputter pre-clean prior to physical vapor deposition, and photoresist stripping during ion implantation. During such plasma processing, devices fabricated on silicon wafers are usually directly exposed to the plasma. Such plasma exposure is known to cause degradation of the gate oxides in MOS devices attributed to electrical charging during the plasma process.
In the plasma ambient, metal or polycrystalline silicon electrodes serve as antennas, thereby collecting ions and electrons during plasma processing. A steady state voltage appears on the electrode due to charge collection and the resulting electrical stress is capable of destroying the underlying gate electrode by oxide breakdown or weakening it by causing charge trapping in the oxide as well as interface trap generation at the silicon dioxide-silicon interface. Since the damaged oxide may cause IC yield loss or become more vulnerable to hot-carrier induced degradation and time-dependent dielectric breakdown, plasma-induced gate oxide degradation constitutes a serious problem in VLSI technology. See, for example, Zheng et al., "A Quick Experimental Technique In Estimating The Cumulative Plasma Charging Current with MOSFET and Determining The Reliability of The Protection Diode In The Plasma Ambient," 1996 1st International Symposium on Plasma Process-Induced Damage (IEEE Cat. No. 96TH8142), 1996, pp. 27-29; H. C. Shin et al., "Thin gate oxide damage due to plasma processing," Semiconductor Science and Technology, April 1996, Vol. 11, No. 4, pp. 463-473; H. Shin et al., "Impact of Plasma Charging Damage and Diode Protection on Scaled Thin Oxide," International Electron Devices Meeting 1993, IEEE Cat. No. 93CH3361-03, 1993, pp. 467-470; and M. C. Chang et al., "Degradation of MOS Transistor Characteristics by Gate Charging Damage During Plasma Processing," International Symposium on VLSI Technology, Systems, and Applications, IEEE Cat. No. 93TH0524-9, 1993, pp. 320-324.
As integration increases and feature size for devices decrease, the thickness of gate oxide layers decreases, thereby exacerbating the adverse impact of plasma charging damage. A conventional approach to the plasma charging damage problem comprises the formation of a protection diode to which the polycrystalline silicon layer, i.e., gate electrode/word line, is connected, thereby providing a discharge path for electrical charging during plasma processing. For example, adverting to FIG. 6, a conventional semiconductor device containing a protection diode comprises substrate 60, such as P-doped silicon, a field oxide shallow trench isolation insulating layer comprising sections 61, and polycrystalline silicon layer 62 formed thereon with a gate oxide layer 63 separating polycrystalline silicon layer 62 from semiconductor substrate 60. Insulating sidewall spacers 64 are formed along side surfaces of polycrystalline silicon layer 62, and a dielectric interlayer 65 is formed thereon. Metal interconnect line 66 electrically connects and, thereby, provides a discharge path between polycrystalline silicon layer 62 and protection diode 67 formed in the semiconductor substrate doped with an N-type impurity.
The conventional structure depicted in FIG. 6 is formed by methodology illustrated in FIGS. 7 and 8. As to FIGS. 6 through 8, similar elements bear similar reference numerals. Adverting to FIG. 7, N-type protection diode 67 is formed by ion implantation, as indicated by arrows 70, typically during ion implantation to form source/drain regions. Subsequently, as shown in FIG. 8, dielectric interlayer 65 is deposited, and through holes 80A and 80B are formed therein, as by anisotropic etching. Through hole 80A exposes an upper surface of polycrystalline silicon layer 62, while through hole 80B exposes a portion of protection diode 67. Subsequently, a layer of metal, typically tungsten, is deposited and etched to form metal interconnect line 66, as shown in FIG. 6, electrically interconnecting polycrystalline silicon layer 62 and protection diode 67.
Conventional practices with respect to a protection diode, such as that illustrated in FIGS. 6 through 8, are attendant with numerous disadvantages, particularly in requiring extra layout area, thereby increasing the total die size and hindering miniaturization. As a result of the consequential increase in precious chip real estate, protection diodes are sparingly used, being reserved for only the most critical areas of the circuit, typically devices connected to bond pads. Accordingly, there exists a need to provide a semiconductor device with a protection diode with minimal or no adverse impact on layout area, thereby enabling the liberal use of protection diodes throughout an integrated circuit.